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1/39 preliminary data may 2002 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. M50FW002 2 mbit (256kb x8, boot block) 3v supply firmware hub flash memory features summary n supply voltage Cv cc = 3 v to 3.6 v for program, erase and read operations Cv pp = 12 v for fast program and fast erase (optional) n two interfaces C firmware hub (fwh) interface for embedded operation with pc chipsets C address/address multiplexed (a/a mux) interface for programming equipment compatibility n firmware hub (fwh) hardware interface mode C 5 signal communication interface supporting read and write operations C hardware write protect pins for block protection C register based read and write protection C 5 additional general purpose inputs for platform design flexibility C synchronized with 33mhz pci clock C multi-byte read operation (1-byte, 16-byte, 32-byte) n programming time C 10 s typical C quadruple byte programming option n 7 memory blocks C 1 boot block (top location) C 4 main blocks and 2 parameter blocks n program/erase controller C embedded byte program, block erase and chip erase algorithms C status register bits n program and erase su spend n for use in pc bios applications figure 1. packages n electronic signature C manufacturer code: 20h C device code: 29h plcc32 (k)
M50FW002 2/39 table of contents summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 firmware hub (fwh) signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 address/address multiplexed (a/a mux) signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 7 supply signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 bus operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 firmware hub (fwh) bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 fwh bus read field definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 fwh bus write field definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 address/address multiplexed (a/a mux) bus operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 a/a mux bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 manufacturer and device codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 firmware hub (fwh) interface configuration registers . . . . . . . . . . . . . . . . . . . . . . 17 lock registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 firmware hub (fwh) general purpose input register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 manufacturer code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 firmware hub register configuration map (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 lock register bit definitions (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 general purpose input register definition (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ac measurement conditions (fwh interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ac measurement conditions (a/a mux interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 device impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 clock characteristics (fwh interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 ac signal timing characteristics (fwh interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 program and erase times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3/39 M50FW002 reset ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 read ac characteristics (a/a mux interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 write ac characteristics (a/a mux interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 plcc32 C 32 lead plastic leaded chip carrier, package mechanical data . . . . . . . . . . . . . . . . . 36 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
M50FW002 4/39 summary description the M50FW002 is a 2 mbit (256kb x8) non-vola- tile memory that can be read, erased and repro- grammed. these operations can be performed using a single low voltage (3.0 to 3.6v) supply. for fast programming and fast erasing in production lines an optional 12v power supply can be used to reduce the programming and the erasing times. the memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. blocks can be protected individually to prevent accidental pro- gram or erase commands from modifying the memory. program and erase commands are writ- ten to the command interface of the memory. an on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. the end of a program or erase operation can be detected and any error conditions identified. the command set required to control the memory is consistent with jedec standards. the device features an asymmetrical blocked ar- chitecture. the device has an array of 7 blocks: n 1 boot block of 16 kbyte n 2 parameter blocks of 8 kbyte each n 1 main block of 32 kbyte n 3 main blocks of 64 kbyte each two different bus interfaces are supported by the memory. the primary interface, the firmware hub (or fwh) interface, uses intels proprietary fwh protocol. this has been designed to remove the need for the isa bus in current pc chipsets; the M50FW002 acts as the pc bios on the low pin count bus for these pc chipsets. the secondary interface, the address/address multiplexed (or a/a mux) interface, is designed to be compatible with current flash programmers for production line programming prior to fitting to a pc motherboard. the memory is delivered with all the bits erased (set to 1). figure 2. plcc connections note: pins 27 and 28 are not internally connected. ai05749 fgpi4 nc fwh4 rfu 17 id1 id0 fwh0 fwh1 fwh2 fwh3 rfu fgpi1 tbl id3 id2 fgpi0 wp 9 clk v ss 1 rp v cc nc fgpi2 rfu 32 v pp v cc M50FW002 fgpi3 ic (v il ) rfu init rfu 25 v ss a1 a0 dq0 a7 a4 a3 a2 a6 a5 a10 rc rp a8 v pp v cc a9 nc w v ss v cc nc dq7 ic (v ih ) g rb dq5 dq1 dq2 dq3 dq4 dq6 v ss a/a mux a/a mux a/a mux a/a mux
5/39 M50FW002 figure 3. logic diagram (fwh interface) table 1. signal names (fwh interface) figure 4. logic diagram (a/a mux interface) table 2. signal names (a/a mux interface) fwh0-fwh3 input/output communications fwh4 input communication frame id0-id3 identification inputs fgpi0-fgpi4 general purpose inputs ic interface configuration rp interface reset init cpu reset clk clock tbl top block lock wp write protect rfu reserved for future use. leave disconnected v cc supply voltage v pp optional supply voltage for fast erase operations v ss ground nc not connected internally ai05747 4 fwh4 fwh0- fwh3 v cc M50FW002 clk v ss 4 ic rp tbl 5 init wp id0-id3 fgpi0- fgpi4 v pp ic interface configuration a0-a10 address inputs dq0-dq7 data inputs/outputs g output enable w write enable rc row/column address select rb ready/busy output rp interface reset v cc supply voltage v pp optional supply voltage for fast program and fast erase operations v ss ground nc not connected internally ai05748 11 rc dq0-dq7 v cc M50FW002 ic v ss 8 g w rb rp a0-a10 v pp
M50FW002 6/39 signal descriptions there are two different bus interfaces available on this part. the active interface is selected before power-up or during reset using the interface con- figuration pin, ic. the signals for each interface are discussed in the firmware hub (fwh) signal descriptions section and the address/address multiplexed (a/a mux) signal descriptions section below. the supply sig- nals are discussed in the supply signal descrip- tions section below. firmware hub (fwh) signal descriptions for the firmware hub (fwh) interface see figure 4, logic diagram, and table 1, signal names. input/output communications (fwh0-fwh3). all input and output communication with the memory take place on these pins. addresses and data for bus read and bus write operations are encoded on these pins. input communication frame (fwh4). the in- put communication frame (fwh4) signals the start of a bus operation. when input communica- tion frame is low, v il , on the rising edge of the clock a new bus operation is initiated. if input communication frame is low, v il , during a bus operation then the operation is aborted. when in- put communication frame is high, v ih , the cur- rent bus operation is proceeding or the bus is idle. identification inputs (id0-id3). the identification inputs select the address that the memory responds to. up to 16 memories can be addressed on a bus. for an address bit to be 0 the pin can be left floating or driven low, v il ; an internal pull-down resistor is included with a value of r il . for an address bit to be 1 the pin must be driven high, v ih ; there will be a leakage current of i li2 through each pin when pulled to v ih ; see table 19. by convention the boot memory must have address 0000 and all additional memories take sequential addresses starting from 0001. general purpose inputs (fgpi0-fgpi4). the gen- eral purpose inputs can be used as digital inputs for the cpu to read. the general purpose input register holds the values on these pins. the pins must have stable data from before the start of the cycle that reads the general purpose input regis- ter until after the cycle is complete. these pins must not be left to float, they should be driven low, v il, or high, v ih . interface configuration (ic). the interface con- figuration input selects whether the firmware hub (fwh) or the address/address multiplexed (a/a mux) interface is used. the chosen interface must be selected before power-up or during a reset and, thereafter, cannot be changed. the state of the interface configuration, ic, should not be changed during operation. to select the firmware hub (fwh) interface the interface configuration pin should be left to float or driven low, v il ; to select the address/address multiplexed (a/a mux) interface the pin should be driven high, v ih . an internal pull-down resistor is included with a value of r il ; there will be a leakage current of i li2 through each pin when pulled to v ih ; see table 19. interface reset (rp ). the interface reset (rp ) input is used to reset the memory. when interface reset (rp ) is set low, v il , the memory is in reset mode: the outputs are put to high impedance and the current consumption is minimized. when rp is set high, v ih , the memory is in normal operation. after exiting reset mode, the memory enters read mode. cpu reset (init ). the cpu reset, init , pin is used to reset the memory when the cpu is reset. it behaves identically to interface reset, rp , and the internal reset line is the logical or (electrical and) of rp and init . clock (clk). the clock, clk, input is used to clock the signals in and out of the input/output communication pins, fwh0-fwh3. the clock conforms to the pci specification. top block lock (tbl ). the top block lock input is used to prevent the top block (block 6) from being changed. when top block lock, tbl , is set low, v il , program and erase operations in the top block have no effect, regardless of the state of the lock register. when top block lock, tbl , is set high, v ih , the protection of the block is determined by the lock register. the state of top block lock, tbl , does not affect the protection of the other blocks (blocks 0 to 5). top block lock, tbl , must be set prior to a pro- gram or erase operation is initiated and must not be changed until the operation completes or un- predictable results may occur. care should be tak- en to avoid unpredictable behavior by changing tbl during program or erase suspend. write protect (wp ). the write protect input is used to prevent the blocks 0 to 5 from being changed. when write protect, wp , is set low, v il , program and erase operations in these blocks have no effect, regardless of the state of the lock register. when write protect, wp , is set high, v ih , the protection of the block is determined by the lock register. the state of write protect, wp , does not affect the protection of the top block (block 6). write protect, wp , must be set prior to a program or erase operation is initiated and must not be changed until the operation completes or unpre-
7/39 M50FW002 dictable results may occur. care should be taken to avoid unpredictable behavior by changing wp during program or erase suspend. reserved for future use (rfu). these pins do not have assigned functions in this revision of the part. they must be left disconnected. address/address multiplexed (a/a mux) signal descriptions for the address/address multiplexed (a/a mux) interface see figure 4, and table 2. address inputs (a0-a10). the address inputs are used to set the row address bits (a0-a10) and the column address bits (a11-a17). they are latched during any bus operation by the row/col- umn address select input, rc . data inputs/outputs (dq0-dq7). the data in- puts/outputs hold the data that is written to or read from the memory. they output the data stored at the selected address during a bus read opera- tion. during bus write operations they represent the commands sent to the command interface of the internal state machine. the data inputs/out- puts, dq0-dq7, are latched during a bus write operation. output enable (g ). the output enable, g , con- trols the bus read operation of the memory. write enable (w ). the write enable, w , controls the bus write operation of the memorys com- mand interface. row/column address select (rc ). the row/ column address select input selects whether the address inputs should be latched into the row address bits (a0-a10) or the column address bits (a11-a17). the row address bits are latched on the falling edge of rc whereas the column address bits are latched on the rising edge. ready/busy output (rb ). the ready/busy pin gives the status of the memorys program/erase controller. when ready/busy is low, v ol , the memory is busy with a program or erase operation and it will not accept any additional program or erase command except the program/erase suspend command. when ready/busy is high, v oh , the memory is ready for any read, program or erase operation. supply signal descriptions the supply signals are the same for both interfac- es. v cc supply voltage. the v cc supply voltage supplies the power for all operations (read, pro- gram, erase etc.). the command interface is disabled when the v cc supply voltage is less than the lockout voltage, v lko . this prevents bus write operations from accidentally damaging the data during power up, power down and power surges. if the program/ erase controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. after v cc becomes valid the command interface is reset to read mode. a 0.1f capacitor should be connected between the v cc supply voltage pins and the v ss ground pin to decouple the current surges from the power supply. both v cc supply voltage pins must be connected to the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations. v pp optional supply voltage. the v pp optional supply voltage pin is used to select the fast program (see the quadruple byte program command description) and fast erase options of the memory and to protect the memory. when v pp < v pplk program and erase operations cannot be performed and an error is reported in the status register if an attempt to change the memory contents is made. when v pp = v cc program and erase operations take place as normal. when v pp = v pph fast program (if a/a mux interface is selected) and fast erase operations are used. any other voltage input to v pp will result in undefined behavior and should not be used. v pp should not be set to v pph for more than 80 hours during the life of the memory. v ss ground. v ss is the reference for all the volt- age measurements. table 3. block addresses size (kbytes) address range block number block type 16 3c000h-3ffffh 6 boot block (top) 8 3a000h-3bfffh 5 parameter block 8 38000h-39fffh 4 parameter block 32 30000h-37fffh 3 main block 64 20000h-2ffffh 2 main block 64 10000h-1ffffh 1 main block 64 00000h-0ffffh 0 main block
M50FW002 8/39 bus operations the two interfaces have similar bus operations but the signals and timings are completely different. the firmware hub (fwh) interface is the usual interface and all of the functionality of the part is available through this interface. only a subset of functions are available through the address/ address multiplexed (a/a mux) interface. follow the section firmware hub (fwh) bus operations below and the section address/ address multiplexed (a/a mux) interface bus operations below for a description of the bus operations on each interface. firmware hub (fwh) bus operations the firmware hub (fwh) interface consists of four data signals (fwh0-fwh3), one control line (fwh4) and a clock (clk). in addition protection against accidental or malicious data corruption can be achieved using two further signals (tbl and wp ). finally two reset signals (rp and init ) are available to put the memory into a known state. the data signals, control signal and clock are designed to be compatible with pci electrical specifications. the interface operates with clock speeds up to 33mhz. the following operations can be performed using the appropriate bus cycles: bus read, bus write, standby, reset and block protection. bus read. bus read operations read from the memory cells, specific registers in the command interface or firmware hub registers. a valid bus read operation starts when input communication frame, fwh4, is low, v il , as clock rises and the correct start cycle is on fwh0-fwh3. on the following clock cycles the host will send the memory id select, address and other control bits on fwh0-fwh3. the memory responds by outputting sync data until the wait-states have elapsed followed by data0-data3 and data4- data7. refer to table 4, fwh bus read field definitions, and figure 5, fwh bus read waveforms (1-byte), for a description of the field definitions for each clock cycle of the transfer. see table 16, ac mea- surement conditions (fwh interface), and figure 10, ac signal timing waveforms (fwh interface), for details on the timings of the signals. bus write. bus write operations write to the command interface or firmware hub registers. a valid bus write operation starts when input communication frame, fwh4, is low, v il , as clock rises and the correct start cycle is on fwh0-fwh3. on the following clock cycles the host will send the memory id select, address, other control bits, data0-data3 and data4-data7 on fwh0-fwh3. the memory outputs sync data until the wait-states have elapsed. refer to table 5, fwh bus write field definitions, and figure 6, fwh bus write waveforms, for a description of the field definitions for each clock cycle of the transfer. see table 16, ac measurement conditions (fwh interface), and figure 10, ac signal timing waveforms (fwh interface), for details on the timings of the signals. bus abort. the bus abort operation can be used to immediately abort the current bus operation. a bus abort occurs when fwh4 is driven low, v il , during the bus operation; the memory will tri-state the input/output communication pins, fwh0- fwh3. note that, during a bus write operation, the command interface starts executing the command as soon as the data is fully received; a bus abort during the final tar cycles is not guaranteed to abort the command; the bus, however, will be released immediately. standby. when fwh4 is high, v ih , the memory is put into standby mode where fwh0-fwh3 are put into a high-impedance state and the supply current is reduced to the standby level, i cc1 . reset. during reset mode all internal circuits are switched off, the memory is deselected and the outputs are put in high-impedance. the memory is in reset mode when interface reset, rp , or cpu reset, init , is low, v il . rp or init must be held low, v il , for t plph . the memory resets to read mode upon return from reset mode and the lock registers return to their default states regardless of their state before reset, see table 12. if rp or init goes low, v il , during a program or erase operation, the operation is aborted and the memory cells affected no longer contain valid data; the memory can take up to t plrh to abort a program or erase operation. block protection. block protection can be forced using the signals top block lock, tbl , and write protect, wp , regardless of the state of the lock registers.
9/39 M50FW002 table 4. fwh bus read field definitions figure 5. fwh bus read waveforms (1-byte) clock cycle number clock cycle count field fwh0- fwh3 memory i/o description 1 1 start 1101b i on the rising edge of clk with fwh4 low, the contents of fwh0-fwh3 indicate the start of a fwh read cycle. 2 1 idsel xxxx i indicates which fwh flash memory is selected. the value on fwh0-fwh3 is compared to the idsel strapping on the fwh flash memory pins to select which fwh flash memory is being addressed. 3-9 7 addr xxxx i a 28-bit address phase is transferred starting with the most significant nibble first. 10 1 msize 0x0xb i indicates how many bytes will be transferred during multi-byte read operations. the fwh flash memory supports 1-byte (0000b), 16-byte (0100b) and 32-byte (0101b) transfers. 11 1 tar 1111b i the host drives fwh0-fwh3 to 1111b to indicate a turnaround cycle. 12 1 tar 1111b (float) o the fwh flash memory takes control of fwh0-fwh3 during this cycle. 13-14 2 wsync 0101b o the fwh flash memory drives fwh0-fwh3 to 0101b (short wait-sync) for two clock cycles, indicating that the data is not yet available. two wait-states are always included. 15 1 rsync 0000b o the fwh flash memory drives fwh0-fwh3 to 0000b, indicating that data will be available during the next clock cycle. 16-17 2 data xxxx o data transfer is two clk cycles, starting with the least significant nibble. 17+ 5(2 n -1) 0 (1-byte) 75 (16-byte) 155 (32-byte) multi- byte 2 wsync + 1 rsync + 2 data o for each subsequent byte of data repeat cycles 13-17 (2wsync + 1rsync + 2data) 2 n -1 times. the fwh flash memory supports n = 0000b (1-byte), n = 0100b (16-byte) and n = 0101b (32-byte) reads. previous +1 1 tar 1111b o the fwh flash memory drives fwh0-fwh3 to 1111b to indicate a turnaround cycle. previous +1 1tar 1111b (float) n/a the fwh flash memory floats its outputs, the host takes control of fwh0-fwh3. ai03437 clk fwh4 fwh0-fwh3 number of clock cycles start idsel addr msize tar sync data tar 11712322
M50FW002 10/39 table 5. fwh bus write field definitions figure 6. fwh bus write waveforms clock cycle number clock cycle count field fwh0- fwh3 memory i/o description 1 1 start 1110b i on the rising edge of clk with fwh4 low, the contents of fwh0-fwh3 indicate the start of a fwh write cycle. 2 1 idsel xxxx i indicates which fwh flash memory is selected. the value on fwh0-fwh3 is compared to the idsel strapping on the fwh flash memory pins to select which fwh flash memory is being addressed. 3-9 7 addr xxxx i a 28-bit address phase is transferred starting with the most significant nibble first. 10 1 msize 0000b i always 0000b (single byte transfer). 11-12 2 data xxxx i data transfer is two cycles, starting with the least significant nibble. 13 1 tar 1111b i the host drives fwh0-fwh3 to 1111b to indicate a turnaround cycle. 14 1 tar 1111b (float) o the fwh flash memory takes control of fwh0-fwh3 during this cycle. 15 1 sync 0000b o the fwh flash memory drives fwh0-fwh3 to 0000b, indicating it has received data or a command. 16 1 tar 1111b o the fwh flash memory drives fwh0-fwh3 to 1111b, indicating a turnaround cycle. 17 1 tar 1111b (float) n/a the fwh flash memory floats its outputs and the host takes control of fwh0-fwh3. ai03441 clk fwh4 fwh0-fwh3 number of clock cycles start idsel addr msize data tar sync tar 11712212
11/39 M50FW002 address/address multiplexed (a/a mux) bus operations the address/address multiplexed (a/a mux) interface has a more traditional style interface. the signals consist of a multiplexed address signals (a0-a10), data signals, (dq0-dq7) and three control signals (rc , g , w ). an additional signal, rp , can be used to reset the memory. the address/address multiplexed (a/a mux) interface is included for use by flash programming equipment for faster factory programming. only a subset of the features available to the firmware hub (fwh) interface are available; these include all the commands but exclude the security features and other registers. the following operations can be performed using the appropriate bus cycles: bus read, bus write, output disable and reset. when the address/address multiplexed (a/a mux) interface is selected all the blocks are unprotected. it is not possible to protect any blocks through this interface. bus read. bus read operations are used to output the contents of the memory array, the electronic signature and the status register. a valid bus read operation begins by latching the row address and column address signals into the memory using the address inputs, a0-a10, and the row/column address select rc . then write enable (w ) and interface reset (rp ) must be high, v ih , and output enable, g , low, v il , in order to perform a bus read operation. the data inputs/outputs will output the value, see figure 12, read ac waveforms (a/a mux interface), and table 24, a/a mux interface read ac characteristics, for details of when the output becomes valid. bus write. bus write operations write to the command interface. a valid bus write operation begins by latching the row address and column address signals into the memory using the address inputs, a0-a10, and the row/column address select rc . the data should be set up on the data inputs/outputs; output enable, g , and interface reset, rp , must be high, v ih and write enable, w , must be low, v il . the data inputs/ outputs are latched on the rising edge of write enable, w . see figure 13, and table 25, a/a mux interface write ac characteristics, for details of the timing requirements. output disable. the data outputs are high-im- pedance when the output enable, g , is at v ih . reset. during reset mode all internal circuits are switched off, the memory is deselected and the outputs are put in high-impedance. the memory is in reset mode when rp is low, v il . rp must be held low, v il for t plph . if rp is goes low, v il , during a program or erase operation, the operation is aborted and the memory cells affected no longer contain valid data; the memory can take up to t plrh to abort a program or erase operation. table 6. a/a mux bus operations table 7. manufacturer and device codes operation g w rp v pp dq7-dq0 bus read v il v ih v ih don't care data output bus write v ih v il v ih v cc or v pph data input output disable v ih v ih v ih don't care hi-z reset v il or v ih v il or v ih v il don't care hi-z operation g w rp a17-a1 a0 dq7-dq0 manufacturer code v il v ih v ih v il v il 20h device code v il v ih v ih v il v ih 29h
M50FW002 12/39 table 8. commands note: x dont care, pa program address, pd program data, a 1,2,3,4 consecutive addresses, ba any address in the block. read memory array : after a read memory array command, read the memory as normal until another command is issued. read status register : after a read status register command, read the status register as normal until another command is issued. read electronic signature : after a read electronic signature command, read manufacturer code, device code until another com- mand is issued. block erase, byte program : after these commands, read the status register until the command completes and another command is issued. quadruple byte program : this command is only valid in a/a mux mode. addresses a 1 , a 2 , a 3 and a 4 must be consecutive addresses differing only for address bit a0 and a1. after this command read the status register until the command completes and another c om- mand is issued. chip erase : this command is only valid in a/a mux mode. after this command, read the status register until the command completes and another command is issued. clear status register : after the clear status register command bits 1, 3, 4 and 5 in the status register are reset to 0. program/erase suspend : after the program/erase suspend command has been accepted, issue read memory array, read status register, program (during erase suspend) and program/erase resume commands. program/erase resume : after the program/erase resume command the suspended program/erase operation resumes, read the status register until the program/erase controller completes and the memory returns to read mode. invalid/reserved : do not use invalid or reserved commands. command cycles bus write operations 1st 2nd 3rd 4th 5th addr data addr data addr data addr data addr data read memory array 1 x ffh read status register 1 x 70h read electronic signature 1x 90h 1x 98h program 2x 40hpapd 2x 10hpapd quadruple byte program 5 x 30h a 1 pd a 2 pd a 3 pd a 4 pd chip erase 2 x 80h x 10h block erase 2 x 20h ba d0h clear status register 1 x 50h program/erase suspend 1 x b0h program/erase resume 1 x d0h invalid/reserved 1x 00h 1x 01h 1x 60h 1x 2fh 1x c0h
13/39 M50FW002 command interface all bus write operations to the memory are interpreted by the command interface. commands consist of one or more sequential bus write operations. after power-up or a reset operation the memory enters read mode. the commands are summarized in table 8, commands. refer to table 8 in conjunction with the text descriptions below. read memory array command. the read mem- ory array command returns the memory to its read mode where it behaves like a rom or eprom. one bus write cycle is required to issue the read memory array command and return the memory to read mode. once the command is is- sued the memory remains in read mode until an- other command is issued. from read mode bus read operations will access the memory array. while the program/erase controller is executing a program or erase operation the memory will not accept the read memory array command until the operation completes. read status register command. the read sta- tus register command is used to read the status register. one bus write cycle is required to issue the read status register command. once the command is issued subsequent bus read opera- tions read the status register until another com- mand is issued. see the section on the status register for details on the definitions of the status register bits. read electronic signature command. the read electronic signature command is used to read the manufacturer code and the device code. one bus write cycle is required to issue the read electronic signature command. once the command is issued subsequent bus read operations read the manufacturer code or the device code until another command is issued. after the read electronic signature command is issued the manufacturer code and device code can be read using bus read operations using the addresses in table 9. table 9. read electronic signature program command. the program command can be used to program a value to one address in the memory array at a time. two bus write operations are required to issue the command; the second bus write cycle latches the address and data in the internal state machine and starts the program/erase controller. once the command is issued subsequent bus read operations read the status register. see the section on the status register for details on the definitions of the status register bits. if the address falls in a protected block then the program operation will abort, the data in the memory array will not be changed and the status register will output the error. during the program operation the memory will only accept the read status register command and the program/erase suspend command. all other commands will be ignored. typical program times are given in table 22. note that the program command cannot change a bit set at 0 back to 1 and attempting to do so will not cause any modification on its value. one of the erase commands must be used to set all of the bits in the block to 1. see figure 14, program flowchart and pseudo code, for a suggested flowchart on using the program command. quadruple byte program command. the qua- druple byte program command can be only used in a/a mux mode to program four adjacent bytes in the memory array at a time. the four bytes must differ only for the addresses a0 and a1. programming should not be attempted when v pp is not at v pph . the operation can also be executed if v pp is below v pph , but result could be uncertain. five bus write operations are required to issue the command. the second, the third and the fourth bus write cycle latches respectively the address and data of the first, the second and the third byte in the internal state machine. the fifth bus write cycle latches the address and data of the fourth byte in the internal state machine and starts the program/erase controller. once the command is issued subsequent bus read operations read the status register. see the section on the status register for details on the definitions of the status register bits. during the quadruple byte program operation the memory will only accept the read status register command and the program/erase suspend com- mand. all other commands will be ignored. typical quadruple byte program times are given in table 22. note that the quadruple byte program command cannot change a bit set to 0 back to 1 and attempting to do so will not cause any modification on its value. an erase command must be used to set all of the bits in the block to 1. see figure 15, quadruple byte program flow- chart and pseudo code (a/a mux interface only), code address data manufacturer code 00000h 20h device code 00001h 29h
M50FW002 14/39 for a suggested flowchart on using the quadruple byte program command. chip erase command. the chip erase com- mand can be used in a/a mux mode to erase the entire chip at a time. erasing should not be at- tempted when v pp is not at v pph . the operation can also be executed if v pp is below v pph , but re- sult could be uncertain. two bus write operations are required to issue the command and start the program/erase controller. once the command is issued, subsequent bus read operations read the status register. (see the section on the status register for details of the definitions of the status register bits.) during the chip erase operation, the memory only accepts the read status register command. all other commands are ignored. typical chip erase times are given in table 22. the chip erase command sets all of the bits in the memory to 1. see figure 17, chip erase flow- chart and pseudo code, for a suggested flowchart when using the chip erase command. block erase command. the block erase com- mand can be used to erase a block. two bus write operations are required to issue the command; the second bus write cycle latches the block address in the internal state machine and starts the pro- gram/erase controller. once the command is is- sued subsequent bus read operations read the status register. see the section on the status register for details on the definitions of the status register bits. if the block is protected then the erase operation will abort, the data in the block will not be changed and the status register will output the error. during the erase operation the memory only accepts the read status register command and the program/erase suspend command. all other commands are ignored. typical erase times are given in table 22. the erase command sets all of the bits in the block to 1. all previous data in the block is lost. see figure 18, for a suggested flowchart on using the erase command. clear status register command. the clear sta- tus register command can be used to reset bits 1, 3, 4 and 5 in the status register to 0. one bus write is required to issue the clear status register command. once the command is issued the mem- ory returns to its previous mode, subsequent bus read operations continue to output the same data. the bits in the status register are sticky and do not automatically return to 0 when a new program or erase command is issued. if an error occurs then it is essential to clear any error bits in the sta- tus register by issuing the clear status register command before attempting a new program or erase command. program/erase suspend command. the pro- gram/erase suspend comm and can be used to pause a program or erase operation. one bus write cycle is required to issue the program/erase suspend command and pause the program/erase controller. once the command is issued it is nec- essary to poll the program/erase controller status bit to find out when the program/erase controller has paused; no other commands will be accepted until the program/erase controller has paused. after the program/erase controller has paused, the memory will continue to output the status reg- ister until another command is issued. during the polling period between issuing the program/erase suspend command and the program/erase controller pausing it is possible for the operation to complete. once program/erase controller status bit indicates that the program/ erase controller is no longer active, the program suspend status bit or the erase suspend status bit can be used to determine if the operation has completed or is suspended. for timing on the delay between issuing the program/erase suspend command and the program/erase controller pausing see table 22. during program/erase suspend the read memory array, read status register, read electronic signature and program/erase resume commands will be accepted by the command interface. additionally, if the suspended operation was erase then the program command will also be accepted; only the blocks not being erased may be read or programmed correctly. see figures 16, program suspend and resume flowchart, and pseudo code, and 19, erase suspend and resume flowchart, and pseudo code, for suggested flowcharts on using the program/erase suspend command. program/erase resume command. the pro- gram/erase resume command can be used to re- start the program/erase controller after a program/erase suspend has paused it. one bus write cycle is required to issue the program/erase resume command. once the command is issued subsequent bus read operations read the status register.
15/39 M50FW002 status register the status register provides information on the current or previous program or erase operation. different bits in the status register convey different information and errors on the operation. to read the status register the read status register command can be issued. the status register is automatically read after program, erase and program/erase resume commands are issued. the status register can be read from any address. the status register bits are summarized in table 10, status register bits. refer to table 10 in con- junction with the text descriptions below. program/erase controller status (bit 7). the pro- gram/erase controller status bit indicates whether the program/erase controller is active or inactive. when the program/erase controller status bit is 0, the program/erase controller is active; when the bit is 1, the program/erase controller is inac- tive. the program/erase controller status is 0 imme- diately after a program/erase suspend command is issued until the program/erase controller paus- es. after the program/erase controller pauses the bit is 1. during program and erase operation the pro- gram/erase controller status bit can be polled to find the end of the operation. the other bits in the status register should not be tested until the pro- gram/erase controller completes the operation and the bit is 1. after the program/erase controller completes its operation the erase status, program status, v pp status and block protection status bits should be tested for errors. erase suspend status (bit 6). the erase sus- pend status bit indicates that an erase operation has been suspended and is waiting to be re- sumed. the erase suspend status should only be considered valid when the program/erase con- troller status bit is 1 (program/erase controller inactive); after a program/erase suspend com- mand is issued the memory may still complete the operation rather than entering the suspend mode. when the erase suspend status bit is 0 the pro- gram/erase controller is active or has completed its operation; when the bit is 1 a program/erase suspend command has been issued and the memory is waiting for a program/erase resume command. when a program/erase resume command is is- sued the erase suspend status bit returns to 0. erase status (bit 5). the erase status bit can be used to identify if the memory has applied the maximum number of erase pulses to the block and still failed to verify that the block has erased cor- rectly. the erase status bit should be read once the program/erase controller status bit is 1 (pro- gram/erase controller inactive). when the erase status bit is 0 the memory has successfully verified that the block has erased cor- rectly; when the erase status bit is 1 the pro- gram/erase controller has applied the maximum number of pulses to the block and still failed to ver- ify that the block has erased correctly. once the erase status bit is set to 1 it can only be reset to 0 by a clear status register command or a hardware reset. if it is set to 1 it should be reset before a new program or erase command is is- sued, otherwise the new command will appear to fail. program status (bit 4). the program status bit can be used to identify if the memory has applied the maximum number of program pulses to the byte and still failed to verify that the byte has pro- grammed correctly. the program status bit should be read once the program/erase controller status bit is 1 (program/erase controller inactive). when the program status bit is 0 the memory has successfully verified that the byte has pro- grammed correctly; when the program status bit is 1 the program/erase controller has applied the maximum number of pulses to the byte and still failed to verify that the byte has programmed cor- rectly. once the program status bit is set to 1 it can only be reset to 0 by a clear status register com- mand or a hardware reset. if it is set to 1 it should be reset before a new program or erase command is issued, otherwise the new command will appear to fail. v pp status (bit 3). the v pp status bit can be used to identify an invalid voltage on the v pp pin during program and erase operations. the v pp pin is only sampled at the beginning of a program or erase operation. indeterminate results can oc- cur if v pp becomes invalid during a program or erase operation. when the v pp status bit is 0 the voltage on the v pp pin was sampled at a valid voltage; when the v pp status bit is 1 the v pp pin has a voltage that is below the v pp lockout voltage, v pplk , the memory is protected; program and erase opera- tion cannot be performed. once the v pp status bit set to 1 it can only be re- set to 0 by a clear status register command or a hardware reset. if it is set to 1 it should be reset before a new program or erase command is is- sued, otherwise the new command will appear to fail.
M50FW002 16/39 program suspend status (bit 2). the program suspend status bit indicates that a program oper- ation has been suspended and is waiting to be re- sumed. the program suspend status should only be considered valid when the program/erase controller status bit is 1 (program/erase control- ler inactive); after a program/erase suspend com- mand is issued the memory may still complete the operation rather than entering the suspend mode. when the program suspend status bit is 0 the program/erase controller is active or has complet- ed its operation; when the bit is 1 a program/ erase suspend command has been issued and the memory is waiting for a program/erase re- sume command. when a program/erase resume command is is- sued the program suspend status bit returns to 0. block protection status (bit 1). the block pro- tection status bit can be used to identify if the pro- gram or erase operation has tried to modify the contents of a protected block. when the block pro- tection status bit is to 0 no program or erase op- erations have been attempted to protected blocks since the last clear status register command or hardware reset; when the block protection status bit is 1 a program or erase operation has been at- tempted on a protected block. once it is set to 1 the block protection status bit can only be reset to 0 by a clear status register command or a hardware reset. if it is set to 1 it should be reset before a new program or erase command is issued, otherwise the new command will appear to fail. using the a/a mux interface the block protection status bit is always 0. reserved (bit 0). bit 0 of the status register is reserved. its value should be masked. table 10. status register bits note: 1. for program operations during erase suspend bit 6 is 1, otherwise bit 6 is 0. operation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 program active 0 x 1 0 0 0 0 0 program suspended 1 x 1 0 0 0 1 0 program completed successfully 1 x 1 0 0 0 0 0 program failure due to v pp error 1 x 1 0 0 1 0 0 program failure due to block protection (fwh interface only) 1 x 1 0 0 0 0 1 program failure due to cell failure 1 x 1 0 1 0 0 0 erase active 0 0 0 0 0 0 0 block erase suspended 1 1 0 0 0 0 0 erase completed successfully 1 0 0 0 0 0 0 erase failure due to v pp error 1 0 0 0 1 0 0 block erase failure due to block protection (fwh interface only) 1 0 0 0 0 0 1 erase failure due to failed cell(s) 1 0 1 0 0 0 0
17/39 M50FW002 firmware hub (fwh) interface configuration registers when the firmware hub interface is selected sev- eral additional registers can be accessed. these registers control the protection status of the blocks, read the general purpose input pins and identify the memory using the electronic signature codes. see table 11 for the memory map of the configuration registers. lock registers the lock registers control the protection status of the blocks. each block has its own lock register. three bits within each lock register control the protection of each block, the write lock bit, the read lock bit and the lock down bit. the lock registers can be read and written, though care should be taken when writing as, once the lock down bit is set, 1, further modifications to the lock register cannot be made until cleared, to 0, by a reset or power-up. see table 12 for details on the bit definitions of the lock registers. write lock. the write lock bit determines whether the contents of the block can be modified (using the program or erase command). when the write lock bit is set, 1, the block is write pro- tected; any operations that attempt to change the data in the block will fail and the status register will report the error. when the write lock bit is re- set, 0, the block is not write protected through the lock register and may be modified unless write protected through some other means. when v pp is less than v pplk all blocks are pro- tected and cannot be modified, regardless of the state of the write lock bit. if top block lock, tbl , is low, v il , then the top block (block 6) is write protected and cannot be modified. similarly, if write protect, wp , is low, v il , then the blocks 0 to 5 are write protected and cannot be modified. after power-up or reset the write lock bit is al- ways set to 1 (write protected). read lock. the read lock bit determines whether the contents of the block can be read (from read mode). when the read lock bit is set, 1, the block is read protected; any operation that attempts to read the contents of the block will read 00h instead. when the read lock bit is reset, 0, read operations in the block return the data pro- grammed into the block as expected. after power-up or reset the read lock bit is al- ways reset to 0 (not read protected). lock down. the lock down bit provides a mechanism for protecting software data from sim- ple hacking and malicious attack. when the lock down bit is set, 1, further modification to the write lock, read lock and lock down bits cannot be performed. a reset or power-up is required be- fore changes to these bits can be made. when the lock down bit is reset, 0, the write lock, read lock and lock down bits can be changed. firmware hub (fwh) general purpose input register the firmware hub (fwh) general purpose input register holds the state of the firmware hub inter- face general purpose input pins, fgpi0-fgpi4. when this register is read, the state of these pins is returned. this register is read-only and writing to it has no effect. the signals on the firmware hub interface gener- al purpose input pins should remain constant throughout the whole bus read cycle in order to guarantee that the correct data is read. manufacturer code register reading the manufacturer code register returns the manufacturer code for the memory. the man- ufacturer code for stmicroelectronics is 20h. this register is read-only and writing to it has no effect. device code register reading the device code register returns the de- vice code for the memory (29h). this register is read-only and writing to it has no effect.
M50FW002 18/39 table 11. firmware hub register configuration map (1) mnemonic register name memory address default value access t_block_lk top block lock register (block 6) fbfc002h 01h r/w t_minus01_lk top block [-1] lock register (block 5) fbfa002h 01h r/w t_minus02_lk top block [-2] lock register (block 4) fbf8002h 01h r/w t_minus03_lk top block [-3] lock register (block 3) fbf0002h 01h r/w t_minus04_lk top block [-4] lock register (block 2) fbe0002h 01h r/w t_minus05_lk top block [-5] lock register (block 1) fbd0002h 01h r/w t_minus06_lk top block [-6] lock register (block 0) fbc0002h 01h r/w fgpi_reg firmware hub (fwh) general purpose input register fbc0100h n/a r manuf_reg manufacturer code register fbc0000h 20h r dev_reg device code register fbc0001h 29h r
19/39 M50FW002 table 12. lock register bit definitions (1) note: 1. applies to top block lock register (t_block_lk) and top block [-1] lock register (t_minus01_lk) to top block [-6] lock r eg- ister (t_minus06_lk). table 13. general purpose input register definition (1) note: 1. applies to the general purpose input register (fgpi_reg). bit bit name value function 7-3 reserved 2 read-lock 1 bus read operations in this block always return 00h. 0 bus read operations in this block return the memory array contents. (default value). 1 lock-down 1 changes to the read-lock bit and the write-lock bit cannot be performed. once a 1 is written to the lock-down bit it cannot be cleared to 0; the bit is always reset to 0 following a reset (using rp or init ) or after power-up. 0 read-lock and write-lock can be changed by writing new values to them. (default value). 0 write-lock 1 program and erase operations in this block will set an error in the status register. the memory contents will not be changed. (default value). 0 program and erase operations in this block are executed and will modify the block contents. bit bit name value function 7-5 reserved 4 fgpi4 1 input pin fgpi4 is at v ih 0 input pin fgpi4 is at v il 3 fgpi3 1 input pin fgpi3 is at v ih 0 input pin fgpi3 is at v il 2 fgpi2 1 input pin fgpi2 is at v ih 0 input pin fgpi2 is at v il 1 fgpi1 1 input pin fgpi1 is at v ih 0 input pin fgpi1 is at v il 0 fgpi0 1 input pin fgpi0 is at v ih 0 input pin fgpi0 is at v il
M50FW002 20/39 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause per- manent damage to the device. exposure to abso- lute maximum rating conditions for extended periods may affect device reliability. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 14. absolute maximum ratings note: 1. minimum voltage may undershoot to C2v during transition and for less than 20ns during transitions. 2. maximum voltage may overshoot to v cc +2v during transition and for less than 20ns during transitions. symbol parameter min max unit t bias temperature under bias C50 125 c t stg storage temperature C65 150 c v io input or output voltage (1,2) C0.6 v cc +0.6 v v cc supply voltage C0.6 4 v v pp program voltage C0.6 13 v
21/39 M50FW002 dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristic tables that follow are de- rived from tests performed under the measure- ment conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame- ters. table 15. operating conditions figure 7. ac measurement i/o waveform (fwh interface) table 16. ac measurement conditions (fwh interface) symbol parameter min. max. unit v cc supply voltage 3.0 3.6 v t a ambient operating temperature (range 1) 0 70 c ambient operating temperature (range 5) C20 85 c symbol parameter min. max. unit c l load capacitance 10 pf input rise and fall times 1.4 ns input pulse voltages 0.2v cc to 0.6v cc v input and output timing reference voltages 0.4v cc v ai03404 0.6 v cc 0.2 v cc 0.4 v cc i o > i lo i o < i lo i o < i lo input and output ac testing waveform output ac tri-state testing waveform
M50FW002 22/39 figure 8. ac measurement i/o waveform (a/a mux interface) table 17. ac measurement conditions (a/a mux interface) table 18. device impedance note: 1. t a =25c, f=1 mhz 2. sampled only, not 100% tested 3. see pci specification symbol parameter min. max. unit c l load capacitance 30 pf input rise and fall times 10 ns input pulse voltages 0 to 3 v input and output timing reference voltages 1.5 v symbol parameter 1 test condition min max unit c in input capacitance 2 v in = 0v 13 pf c clk clock capacitance 2 v in = 0v 312pf l pin recommended pin inductance 3 20 nh ai01417 3v 0v 1.5v
23/39 M50FW002 table 19. dc characteristics note: 1. sampled only, not 100% tested. 2. input leakage currents include high-z output leakage for all bi-directional buffers with tri-state outputs. symbol parameter interface test condition min max unit v ih input high voltage fwh 0.5 v cc v cc + 0.5 v a/a mux 0.7 v cc v cc + 0.3 v v il input low voltage fwh C0.5 0.3 v cc v a/a mux -0.5 0.8 v v ih (init ) init input high voltage fwh 1.35 v cc + 0.5 v v il (init ) init input low voltage fwh C0.5 0.2 v cc v i li (2) input leakage current 0v v in v cc 10 a i li2 ic, idx input leakage current ic, id0, id1, id2, id3 = v cc 200 a r il ic, idx input pull low resistor 20 100 k w v oh output high voltage fwh i oh = C500 a 0.9 v cc v a/a mux i oh = C100 a v cc C 0.4 v v ol output low voltage fwh i ol = 1.5ma 0.1 v cc v a/a mux i ol = 1.8ma 0.45 v i lo output leakage current 0v v out v cc 10 a v pp1 v pp voltage 3 3.6 v v pph v pp voltage (fast program/fast erase) 11.4 12.6 v v pplk (1) v pp lockout voltage 1.5 v v lko (1) v cc lockout voltage 1.8 2.3 v i cc1 supply current (standby) fwh fwh4 = 0.9 v cc , v pp = v cc all other inputs 0.9 v cc to 0.1 v cc v cc = 3.6v, f(clk) = 33mhz 100 m a i cc2 supply current (standby) fwh fwh4 = 0.1 v cc , v pp = v cc all other inputs 0.9 v cc to 0.1 v cc v cc = 3.6v, f(clk) = 33mhz 10 ma i cc3 supply current (any internal operation active) fwh v cc = v cc max, v pp = v cc f(clk) = 33mhz i out = 0ma 60 ma i cc4 supply current (read) a/a mux g = v ih , f = 6mhz 20 ma i cc5 (1) supply current (program/erase) a/a mux program/erase controller active 20 ma i pp v pp supply current (read/standby) v pp > v cc 400 m a i pp1 (1) v pp supply current (program/erase active) v pp = v cc 40 ma v pp = 12v 5% 15 ma
M50FW002 24/39 table 20. clock characteristics (fwh interface) note: 1. devices on the pci bus must work with any clock frequency between dc and 33mhz. below 16mhz devices may be guaranteed by design rather than tested. refer to pci specification. figure 9. clock waveform (fwh interface) symbol parameter test condition value unit t cyc clk cycle time (1) min 30 ns t high clk high time min 11 ns t low clk low time min 11 ns clk slew rate peak to peak min 1 v/ns max 4 v/ns ai03403 thigh tlow 0.6 v cc tcyc 0.5 v cc 0.4 v cc 0.3 v cc 0.2 v cc 0.4 v cc , p-to-p (minimum)
25/39 M50FW002 table 21. ac signal timing characteristics (fwh interface) note: 1. the timing measurements for active/float transitions are defined when the current through the pin equals the leakage cur rent spec- ification. 2. applies to all inputs except clk. figure 10. ac signal timing waveforms (fwh interface) symbol pci symbol parameter test condition value unit t chqv t val clk to data out min 2 ns max 11 ns t chqx (1) t on clk to active (float to active delay) min 2 ns t chqz t off clk to inactive (active to float delay) max 28 ns t av ch t dvch t su input set-up time (2) min 7 ns t chax t chdx t h input hold time (2) min 0 ns ai03405 tchqv tchqx tchqz tchdx valid fwh0-fwh3 tdvch clk valid output data float output data valid input data
M50FW002 26/39 table 22. program and erase times note: 1. t a = 25c, v cc = 3.3v 2. this time is obtained executing the quadruple byte program command. 3. sampled only, not 100% tested. table 23. reset ac characteristics note: 1. see chapter 4 of the pci specification. parameter interface test condition min typ (1) max unit byte program 10 200 m s quadruple byte program a/a mux v pp = 12v 5% 10 200 m s chip erase a/a mux v pp = 12v 5% 3sec block program (64 kbytes) a/a mux v pp = 12v 5% 0.1 (2) 5sec v pp = v cc 0.4 5 sec block erase (64 kbytes) v pp = 12v 5% 0.75 8 sec v pp = v cc 110sec program/erase suspend to program pause (3) 5 m s program/erase suspend to block erase pause (3) 30 m s symbol parameter test condition value unit t plph rp or init reset pulse width min 100 ns t plrh rp or init low to reset program/erase inactive max 100 ns program/erase active max 30 m s rp or init slew rate (1) rising edge only min 50 mv/ns t phfl rp or init high to fwh4 low fwh interface only min 30 m s t phwl t phgl rp high to write enable or output enable low a/a mux interface only min 50 m s
27/39 M50FW002 figure 11. reset ac waveforms ai03420 rp, init w, g, fwh4 tplph rb tplrh tphwl, tphgl, tphfl
M50FW002 28/39 table 24. read ac characteristics (a/a mux interface) note: 1. g may be delayed up to t chqv C t glqv after the rising edge of rc without impact on t chqv . figure 12. read ac waveforms (a/a mux interface) symbol parameter test condition value unit t avav read cycle time min 250 ns t avcl row address valid to rc low min 50 ns t clax rc low to row address transition min 50 ns t av ch column address valid to rc high min 50 ns t chax rc high to column address transition min 50 ns t chqv (1) rc high to output valid max 150 ns t glqv (1) output enable low to output valid max 50 ns t phav rp high to row address valid min 1 m s t glqx output enable low to output transition min 0 ns t ghqz output enable high to output hi-z max 50 ns t ghqx output hold from output enable high min 0 ns ai03406 tavav tclax tchax tglqx tglqv tghqx valid a0-a10 g dq0-dq7 rc tchqv tghqz column addr valid w rp tphav row addr valid next addr valid tavcl tavch
29/39 M50FW002 table 25. write ac characteristics (a/a mux interface) note: 1. sampled only, not 100% tested. 2. applicable if v pp is seen as a logic input (v pp < 3.6v). figure 13. write ac waveforms (a/a mux interface) symbol parameter test condition value unit t wlwh write enable low to write enable high min 100 ns t dvwh data valid to write enable high min 50 ns t whdx write enable high to data transition min 5 ns t avcl row address valid to rc low min 50 ns t clax rc low to row address transition min 50 ns t av ch column address valid to rc high min 50 ns t chax rc high to column address transition min 50 ns t whwl write enable high to write enable low min 100 ns t chwh rc high to write enable high min 50 ns t vphwh (1) v pp high to write enable high min 100 ns t whgl write enable high to output enable low min 30 ns t whrl write enable high to rb low min 0 ns t qvvpl (1,2) output valid, rb high to v pp low min 0 ns ai04194 tclax tchax twhdx tdvwh valid srd a0-a10 g dq0-dq7 rc tchwh twhrl c1 w r1 tavcl tavch r2 c2 twlwh twhwl rb v pp tvphwh twhgl tqvvpl d in1 d in2 write erase or program setup write erase confirm or valid address and data automated erase or program delay read status register data ready to write another command
M50FW002 30/39 figure 14. program flowchart and pseudo code note: 1. a status check of b1 (protected block), b3 (v pp invalid) and b4 (program error) can be made after each program operation by following the correct command sequence. 2. if an error is found, the status register must be cleared before further program/erase controller operations. write 40h or 10h ai03407 start write address & data read status register yes no b7 = 1 yes no b3 = 0 no b4 = 0 v pp invalid error (1, 2) program error (1, 2) program command: C write 40h or 10h C write address & data (memory enters read status state after the program command) do: Cread status register if program/erase suspend command given execute suspend program loop while b7 = 1 if b3 = 1, v pp invalid error: C error handler if b4 = 1, program error: C error handler yes end yes no b1 = 0 program to protected block error (1, 2) if b1 = 1, program to protected block error: C error handler suspend suspend loop no yes fwh interface only
31/39 M50FW002 figure 15. quadruple byte program flowchart and pseudo code (a/a mux interface only) note: 1. a status check of b3 (v pp invalid) and b4 (program error) can be made after each program operation by following the correct com- mand sequence. 2. if an error is found, the status register must be cleared before further program/erase controller operations. 3. address 1, address 2, address 3 and address 4 must be consecutive addresses differing only for address bits a0 and a1. ai03982 write address 4 & data 4 (3) read status register yes no b7 = 1 yes no b3 = 0 no b4 = 0 v pp invalid error (1, 2) program error (1, 2) quadruple byte program command: C write 30h C write address 1 & data 1 (3) C write address 2 & data 2 (3) C write address 3 & data 3 (3) C write address 4 & data 4 (3) (memory enters read status state after the quadruple byte program command) do: C read status register if program/erase suspend command given execute suspend program loop while b7 = 1 if b3 = 1, v pp invalid error: C error handler if b4 = 1, program error: C error handler end yes suspend suspend loop no yes write 30h start write address 1 & data 1 (3) write address 2 & data 2 (3) write address 3 & data 3 (3)
M50FW002 32/39 figure 16. program suspend and resume flowchart, and pseudo code write 70h ai03408 read status register yes no b7 = 1 yes no b2 = 1 program continues write a read command program/erase suspend command: C write b0h C write 70h do: C read status register while b7 = 1 if b2 = 0 program completed write d0h program/erase resume command: C write d0h to resume the program C if the program operation completed then this is not necessary. the device returns to read as normal (as if the program/erase suspend was not issued). read data from another address start write b0h program complete write ffh read data
33/39 M50FW002 figure 17. chip erase flowchart and pseudo code (a/a mux interface only) note: 1. if an error is found, the status register must be cleared before further program/erase controller operations. write 80h ai04195 start write 10h read status register yes no b7 = 1 yes no b3 = 0 no b4, b5 = 0 v pp invalid error (1) command sequence error (1) chip erase command: C write 80h C write 10h (memory enters read status register after the chip erase command) do: C read status register while b7 = 1 if b3 = 1, v pp invalid error: C error handler if b4, b5 = 1, command sequence error: C error handler yes no b5 = 0 erase error (1) if b5 = 1, erase error: C error handler end yes
M50FW002 34/39 figure 18. block erase flowchart and pseudo code note: 1. if an error is found, the status register must be cleared before further program/erase controller operations. write 20h ai05433 start write block address & d0h read status register yes no b7 = 1 yes no b3 = 0 no b4, b5 = 0 v pp invalid error (1) command sequence error (1) erase command: C write 20h C write block address & d0h (memory enters read status register after the erase command) do: C read status register C if program/erase suspend command given execute suspend erase loop while b7 = 1 if b3 = 1, v pp invalid error: C error handler if b4, b5 = 1, command sequence error: C error handler yes no b5 = 0 erase error (1) yes no suspend suspend loop if b5 = 1, erase error: C error handler end yes no b1 = 0 erase to protected block error (1) if b1 = 1, erase to protected block error: C error handler yes fwh interface only
35/39 M50FW002 figure 19. erase suspend and resume flowchart, and pseudo code write 70h ai03410 read status register yes no b7 = 1 yes no b6 = 1 erase continues program/erase suspend command: C write b0h C write 70h do: C read status register while b7 = 1 if b6 = 0, erase completed write d0h read data from another block or program start write b0h erase complete write ffh read data program/erase resume command: C write d0h to resume erase C if the erase operation completed then this is not necessary. the device returns to read as normal (as if the program/erase suspend was not issued).
M50FW002 36/39 package mechanical plcc32 C 32 lead plastic leaded chip carrier, package outline note: drawing is not to scale. plcc32 C 32 lead plastic leaded chip carrier, package mechanical data symbol millimeters inches typ min max typ min max a 3.18 3.56 0.125 0.140 a1 1.53 2.41 0.060 0.095 a2 0.38 C 0.015 C b 0.33 0.53 0.013 0.021 b1 0.66 0.81 0.026 0.032 cp 0.10 0.004 d 12.32 12.57 0.485 0.495 d1 11.35 11.51 0.447 0.453 d2 4.78 5.66 0.188 0.223 d3 7.62 C C 0.300 C C e 14.86 15.11 0.585 0.595 e1 13.89 14.05 0.547 0.553 e2 6.05 6.93 0.238 0.273 e3 10.16 C C 0.400 C C e 1.27 C C 0.050 C C f 0.00 0.13 0.000 0.005 n32 32 r 0.89 C C 0.035 C C plcc-a d e3 e1 e 1 n d1 d3 cp b e2 e b1 a1 a r 0.51 (.020) 1.14 (.045) f a2 e2 d2 d2
37/39 M50FW002 part numbering table 26. ordering information scheme devices are shipped from the factory with the memory content bits erased to 1. for a list of available op- tions (speed, package, etc...) or for further information on any aspect of this device, please contact your nearest st sales office. example: M50FW002 k 1 t device type m50 architecture f = firmware hub interface operating voltage w = 3.0 to 3.6v device function 002 = 2 mbit (256kb x8), boot block package k = plcc32 temperature range 1 = 0 to 70 c 5 = C20 to 85c option t = tape & reel packing
M50FW002 38/39 revision history table 27. document revision history date version revision details 18-dec-2001 -01 document released 22-jan-2002 -02 details of chip erase command added 01-mar-2002 -03 rfu pins must be left disconnected 12-mar-2002 -04 specification of plcc32 package mechanical data revised 31-may-2002 -05 document promoted from product preview to preliminary data
39/39 M50FW002 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - unit ed states. www.st.com

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